A multilayered wiring in a chip is required to be finer along with higher integration and miniaturization in a memory and the like, and it is expected that the most recent flash memory reaches a half pitch of 10 nm or less around 2020. On the other hand, resistivity is rapidly increasing along with the miniaturization due to an increase in inelastic scattering of a generally-used metal wiring of Cu or the like, and is reaching the limit of the material. To the contrary, it is reported that a nano-carbon material such as graphene or carbon nanotube (CNT) has a remarkably longer mean free path or higher mobility also in a finer area than the metals, which is expected as a next-generation fine wiring material. In particular, graphene may form a fine-width wiring in a lithography process well compatible with the existing LSI process, and fine-width integrated wiring based on multilayered graphene by CVD (Chemical Vapor Deposition) is increasingly developed.
A method for manufacturing the fine-width wiring structure using multilayered graphene is basically to pattern entirely-grown catalyst, but there is a problem that a metal material such as Fe, Co or Ni having a capability to dissolve and precipitate carbon at a low temperature is difficult to etch. As a solution thereto, there is proposed a method for performing damascene wiring on a catalyst metal and patterning it thereby to selectively grow carbon on the wiring. A carbon layer is precipitated with excellent selectivity on the catalyst metal layer of Ni or the like in a trench patterned by CMP. However, according to the present method, a metal barrier layer for holding Ni is required inside a wiring trench, and a thickness thereof is required on both sides of the trench, which is a remaining problem against finer width.